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| 1/58 april 1999 n high performance cpu high performance 16-bit cpu with 4-stage pipeline 80ns instruction cycle time @ 25mhz cpu clock 400ns multiplication (16 16 bits) 800ns division (32 / 16 bit) enhanced boolean bit manipulation fa- cilities additional instructions to support hll and operating systems single-cycle context switching sup- port n memory organization up to 16 mbytes linear address space for code and data (1mbyte with ssp used) 1 kbytes on-chip ram 128 kbytes on-chip flash memory 4 independently erasable banks of flash n fast and flexible bus programmable ebc 8-bit or 16-bit external data bus multiplexed or demultiplexed exter- nal address/data buses five programmable chip-select signals hold and hold-acknowledge bus arbi- tration support n on-chip bootstrap loader n fail-safe protection programmable watchdog timer oscillator watchdog n interrupt 8-channel interrupt-driven single-cy- cle data transfer facilities via periph- eral event controller (pec) 16-priority-level interrupt system with 20 sources, sample-rate down to 40ns n timers two general purpose timer units with 5 timers n clock generation on-chip pll direct or prescaled clock input n up to 77 general purpose i/o lines n idle and power down modes n serial channels synchronous/asynchronous high-speedsynchronous serial portssp n development support c-compilers, macro-assembler packag- es, emulators, evaluation boards, hll-debuggers, simulators, logic ana- lyzer disassemblers, programming boards n package 100-pin thin quad flat pack (tqfp) pqfp100 (14 x 14 mm) (plastic quad flat pack) p.0 p.1 p.4 p.6 p.5 p.3 p.2 ssp brg gpt1&2 asc brg flash cpu ram watchdog interrupt controller pec pll ebc ST10F163 16-bit mcu with 128kbyte flash memory this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice.
ST10F163 2/58 i introduction ........................................................................................................ 4 ii pin data ............................................................................................................. 5 iii functional description ................................................................................... 9 iv memory organization ....................................................................................... 10 v flash memory ...................................................................................................... 10 v.1 programming/erasing with st embedded algorithm kernel ............ 11 v.1.1 return values ............................................................................................................. 1 3 v.1.2 programming examples .............................................................................................. 13 v.2 flash memory configuration......................................................................... 14 v.3 flash protection ............................... ................................................................. 14 vi external bus controller .............................................................................. 15 vi.1 programmable chip select timing control ............................................. 15 vii central processing unit (cpu) ..................................................................... 17 viii interrupt system ............................................................................................... 18 ix general purpose timer (gpt) unit ........................................... .................... 20 ix.1 gpt1 ....................................................................................................................... .... 20 ix.2 gpt2 ....................................................................................................................... .... 20 x parallel ports ............................................................................... .................... 23 xi serial channels ................................................................................................. 23 xii watchdog timer .................................................................................................. 25 xiii oscillator watchdog (owd) ......................................................................... 25 xiv instruction set summary ................................. .............................................. 26 xv special function register overview ......................................................... 28 xvi electrical characteristics ........ ................................................................. 31 xvi.1 absolute maximum ratings ............. ................................................................. 31 xvi.2 parameter interpretation.............................................................................. 31 xvi.3 dc characteristics ............................................................................................ 31 xvi.4 ac characteristics............................................................................................. 33 xvi.4.1 test waveforms .......................................................................................................... 3 3 xvi.4.2 definition of internal timing ......................................................................................... 34 xvi.4.3 clock generation modes ............................................................................................. 34 xvi.4.4 prescaler operation .................................................................................................... 35 xvi.4.5 direct drive ............................................................................................................. .... 35 xvi.4.6 oscillator watchdog (owd) ................................................................... .................... 35 table of contents page ST10F163 3/58 xvi.4.7 phase locked loop ...................................................................................................... 35 xvi.4.8 memory cycle variables .............................................................................................. 36 xvi.4.9 external clock drive xtal1 .......................................... .............................................. 37 xvi.4.10 multiplexed bus ...................................................................................... ................... .38 xvi.4.11 demultiplexed bus ...................................................................................................... 4 4 xvi.4.12 clkout and ready ................................................................................................ 50 xvi.4.13 external bus arbitration ........................................................................... .................... 52 xvi.4.14 synchronous serial port timing ................................................................................... 54 xvii package mechanical data ........................................................................... 56 xviii ordering information ...................................................................................... 56 xix revision history ................................ ................................................................. 57 ST10F163 4/58 i - introduction the ST10F163 is a flash derivative of the stmicroelectronics st10 family of 16-bit micro- controllers. it combines high cpu performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced io-capabilities. 128kbytes of an electrically eras- able and re-programmable flash eprom is pro- vided on-chip. figure 1 : logic symbol xtal1 rstin xtal2 rstout nmi ea ready ale rd wr/wrl port 5 6-bit port 6 8-bit port 4 8-bit port 3 15-bit port 2 8-bit port 1 16-bit port 0 16-bit v dd v ss ST10F163 ST10F163 5/58 ii - pin data figure 2 : tqfp pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100999897969594939291908988878685848382818079787776 p5.13/t5in p5.14/t4eud p5.15/t2eud v ss xtal1 xtal2 v dd p3.0 p3.1/t6out p3.2/capin p3.3/t3out p3.4/t3eud p3.5/t4in p3.6/t3in p3.7/t2in p3.8 p3.9 p3.10/txd0 p3.11/rxd0 p3.12/bhe/wrh p3.13 p3.15/clkout p4.0/a16 p4.1/a17 p4.2/a18 p1h.6/a14 p1h.5/a13 p1h.4/a12 p1h.3/a11 p1h.2/a10 v ss v dd p1h.1/a9 p1h.0/a8 p1l.7/a7 p1l.6/a6 p1l.5/a5 p1l.4/a4 p1l.3/a3 p1l.2/a2 p1l.1/a1 p1l.0/a0 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 p0h.4/ad12 p0h.3/ad11 p0h.2/ad10 p0h.1/ad9 p0h.0/ad8 p5.12/t6in p5.11/t5eud p5.10/t6eud p2.15/ex7in p2.14/ex6in p2.13/ex5in p2.12/ex4in p2.11/ex3in p2.10/ex2in p2.9/ex1in p2.8/ex0in p6.7/breq p6.6/hlda p6.5/hold p6.4/cs4 p6.3/cs3 p6.2/cs2 p6.1/cs1 p6.0/cs0 nmi rstout rstin v dd v ss p1h.7/a15 p4.3/a19 v ss v dd p4.4/a20/sspce1 p4.5/a21/sspce0 p4.6/a22/sspdat p4.7/a23/sspclk rd wr/wrl ready ale ea v dd v ss v pp p0l.0/ad0 p0l.1/ad1 p0l.2/ad2 p0l.3/ad3 p0l.4/ad4 p0l.5/ad5 p0l.6/ad6 p0l.7/ad7 v dd v ss ST10F163 ST10F163 6/58 table 1 : pin definitions and functions symbol pin number( tqfp) input (i) output (o) function p5.10 p5.15 98-100 1- 3 i i 6-bit input-only port with schmitt-trigger characteristics. port 5 pins also serve as timer inputs: 98 i p5.10 t6eud gpt2 timer t6 ext.up/down ctrl.input 99 i p5.11 t5eud gpt2 timer t5 ext.up/down ctrl.input 100 i p5.12 t6in gpt2 timer t6 count input 1 i p5.13 t5in gpt2 timer t5 count input 2 i p5.14 t4eud gpt1 timer t4 ext.up/down ctrl.input 3 i p5.15 t2eud gpt1 timer t2 ext.up/down ctrl.input xtal1 5 i xtal1: input to the oscillator amplifier and input to the internal clock generator xtal2 6 o xtal2: output of the oscillator amplifier circuit. to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. p3.0 p3.13, p3.15 8- 21 22 i/o i/o 15-bit (p3.14 is missing) bidirectional i/o port, bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 3 outputs can be configured as push/pull or open drain drivers. the following port 3 pins have alternate functions: 9 o p3.1 t6out gpt2 timer t6 toggle latch output 10 i p3.2 capin gpt2 register caprel capture input 11 io p3.3 t3out gpt1 timer t3 toggle latch output 12 i p3.4 t3eud gpt1 timer t3 ext.up/down ctrl.input 13 i p3.5 t4in gpt1 timer t4 input for count/gate/reload/capture 14 i p3.6 t3in gpt1 timer t3 count/gate input 15 i p3.7 t2in gpt1 timer t2 input for count/gate/reload/capture 18 o p3.10 txd0 asc0 clock/data output (asyn./syn.) 19 i/o p3.11 rxd0 asc0 data input (asyn.) or i/o (syn.) 20 o p3.12 bhe ext. memory high byte enable signal, o wrh ext. memory high byte write strobe 22 o p3.15 clkout system clock output (=cpu clock) ST10F163 7/58 p4.0 p4.7 23-26 29-32 i/o 8-bit bidirectional i/o port, bit-wise programmable for input or output via direc- tion bits. for a pin configured as input, the output driver is put into high-imped- ance state. for external bus configuration, port 4 can be used to output the segment address lines: 23 o p4.0 a16 least significant segment addr. line ... ... ... ... ... 26 o p4.3 a19 segment address line 29 o p4.4 a20 segment address line o sspce1 ssp chip enable line 1 30 o p4.5 a21 segment address line o sspce0 ssp chip enable line 0 31 o p4.6 a22 segment address line i/o sspdat ssp data input/output line 32 o p4.7 a23 most significant segment addr. line o sspclk ssp clock output line rd 33 o external memory read strobe. rd is activated for every external instruction or data read access. wr/wrl 34 o external memory write strobe. in wr-mode this pin is activated for every external data write access. in wrl-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in register syscon for mode selection. ready 35 i ready input. when the ready function is enabled, a high level at this pin dur- ing an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ale 36 o address latch enable output. can be used for latching the address into exter- nal memory or an address latch in the multiplexed bus modes. ea 37 i external access enable pin. a low level at this pin during and after reset forces the device to begin instruction execution out of external memory. a high level forces execution out of the internal flash eprom. port0: p0l.0-p0l.7 p0h.0-p0h.7 41-48 51-58 i/o two 8-bit bidirectional i/o ports p0l and p0h, bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. in case of an external bus configuration, port0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. table 1 : pin definitions and functions (continued) symbol pin number( tqfp) input (i) output (o) function demultiplexed bus modes data path width: 8-bit 16-bit p0l.0 p0l.7: d0 d7 d0 - d7 p0h.0 p0h.7: i/o d8 - d15 multiplexed bus modes data path width: 8-bit 16-bit p0l.0 p0l.7: ad0 ad7 ad0 - ad7 p0h.0 p0h.7: a8 a15 ad8 ad15 ST10F163 8/58 port1: p1l.0-p1l.7 p1h.0-p1h.7 59-66 67, 68 71-76 i/o two 8-bit bidirectional i/o ports p1l and p1h, bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port1 is used as the 16-bit address bus (a) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. rstin 79 i reset input with schmitt-trigger characteristics. a low level at this pin for a specified duration while the oscillator is running resets the device. an internal pullup resistor permits power-on reset using only a capacitor connected to v ss . rstout 80 o internal reset indication output. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. rstout remains low until the einit (end of initialization) instruction is executed. nmi 81 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instruc- tion is executed, the nmi pin must be low in order to force the st10r65 to go into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. p6.0-p6.7 82-89 i/o 8-bit bidirectional i/o port, bit-wise programmable for input or output via direc- tion bits. for a pin configured as input, the output driver is put into high-imped- ance state. port 6 outputs can be configured as push/pull or open drain drivers. the following port 6 pins have alternate functions: 82 o p6.0 cs0 chip select 0 output ... ... ... ... ... 86 o p6.4 cs4 chip select 4 output 87 i p6.5 hold external master hold request input (master mode: o, slave mode: i) 88 i/o p6.6 hlda hold acknowledge output 89 o p6.7 breq bus request output p2.8 p2.15 90 - 97 i/o port 2 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port 2 outputs can be configured as push/pull or open drain drivers. the following port 2 pins also serve for alternate functions: 90 i p2.8 ex0in fast external interrupt 0 input ... ... ... ... ... 97 i p2.15 ex7in fast external interrupt 7 input v pp 40 - flash programming voltage. this pin accepts the programming voltage for the on-chip flash eprom. in the ST10F163, bit 4of syscon register serves as an enable/disable control for the owd. v dd 7, 28, 38, 49, 69, 78 - digital supply voltage: + 5 v during normal operation and idle mode. > 2.5 v during power down mode v ss 4, 27, 39, 50, 70, 77 - digital ground. table 1 : pin definitions and functions (continued) symbol pin number( tqfp) input (i) output (o) function ST10F163 9/58 iii - functional description the architecture of the ST10F163 combines the advantages of both risc and cisc processors and an advanced peripheral subsystem. the fol- lowing block diagram gives an overview of the dif- ferent on-chip components and of the advanced, high bandwidth internal bus structure. figure 3 : block diagram osc. port 0 port 1 port 4 port 6 port 5 port 3 port 2 ext. bus con- troller ssp brg gpt1 t2 t3 t4 gpt2 t5 t6 asc (usart) brg internal flash memory cpu-core internal ram watchdog interrupt controller 16 16 8 8 8 15 6 32 16 pec 16 16 16 16 pll ST10F163 10/58 iv - memory organization the memory space of the ST10F163 is configured in a von-neumann architecture. code memory, data memory, registers and i/o ports are orga- nized within the same linear address space which includes 16 mbytes. the entire memory space can be accessed bytewise or wordwise. particular portions of the on-chip memory have additionally been made directly bit addressable. 1 kbyte of on-chip ram is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. a register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, , rl7, rh7) general purpose registers (gprs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space). sfrs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for other/future members of the st10 family. in order to meet the needs of system designs where more memory is required than is provided on chip, up to 16 mbytes of external ram and/or rom can be connected to the microcontroller. v - flash memory the ST10F163 provides 128kbytes of on-chip, electrically erasable and re-programmable flash eprom. the flash memory is organized in 32 bit wide blocks. this allows double word instructions to be fetched in one machine cycle. the flash memory can be used for both code and data stor- age. the flash memory is organized into four banks of sizes 8k, 24k, 48k and 48kbytes (table 2). each of these banks can be erased indepen- dently. this prevents unnecessary erasing of the whole flash memory when only a partial erasing is required (see table 2). typical timing characteristics give 80 m s for word or double word programming and 800 ms for block erasing, at 25mhz system clock. the flash memory has a typical endurance of 1000 erasing/program- ming cycles. the flash memory can be pro- grammed, either in a programming board, or in the target system. the code to program or erase the flash memory is executed from an external mem- ory or from the on-chip ram, but not from the flash memory itself. as a flexible and cost-saving alter- native, the on-chip bootstrap loader may be used to load and start the programming code. the following considerations must be taken into account for programming or erasing `on-line' in the target system: while operations are in progress, the flash mem- ory can not be accessed as usual, no branch can be made to the flash memory and no data reads can be taken from the flash memory. if the two first blocks (8kb + 24kb) of the flash memory are mapped to segment 0, no interrupt or hardware trap must occur during program- ming or erasing, as this would require a `forbid- den' branch to the flash memory. a flash memory protection option, when activated, prevents view access to the contents of the rom and the on-chip ram, code operation from within the flash memory continues as normal. during the initialization phase, the first two blocks of the flash memory (8kb + 24kb) can be mapped to seg- ment 0 (addresses 00000h to 07fffh), or to seg- ment 1 (addresses 10000h to 17fffh). this makes it possible to use external memory for addi- tional system flexibility. table 2 : flash memory bank organisation bank addresses (segment 0) addresses (segment 1) size (bytes) 0 1 2 3 000000h to 001fffh 002000h to 007fffh 018000h to 023fffh 024000h to 02ffffh 010000h to 011fffh 012000h to 017fffh 018000h to 023fffh 024000h to 02ffffh 8k 24k 48k 48k ST10F163 11/58 v.1 - programming/erasing with st embedded algorithm kernel in order to secure flash programming and erasing operations, and also to simplify the software development for programming and erasing the flash, the ST10F163 flash is programmed or erased by executing a specific sequence of instructions (called `unlock sequence') with com- mand and parameters loaded into gprs. the unlock sequence' invokes embedded kernel rou- tines that checks the validity of the parameters provided by the user, and decodes the command (programming or erasing) and executes it. when performing a programming command, the embedded algorithm kernel automatically times the program pulse widths (taking in account the cpu period provided as a parameter by the user) and verifies proper cell programming. when performing an erasing command, the embedded algorithm kernel automatically pre-programs the bank to be erased if it is not already programmed. during erase, the embed- ded algorithm kernel automatically times the erase pulse widths (taking in account the cpu period provided as a parameter by the user) and verifies proper cell erasing. to start a program/erase operation, the user's application must perform an `unlock sequence' to trigger the flash st embedded algorithms kernel (steak). before using steak, proper parame- ters must be assigned through the r0-r4 regis- ters. the r0 register is the command register. the other registers handle the address and data to be programmed or sector to be erased. table 3 defines the command sequence. a definition of the codes used in table 3 is given in table 4. note the read status for registers r1 to r3 is not used except for the return values, refer to areturn valueso on page 13 table 3 : command -parameters definition command r0 r1 r2 r3 r4 single word programming 55ash addoff w nu 2tcl double word programming dd4sh addoff dwl dwh 2tcl block programming aa5sh begaddoff endaddoff sourceaddr 2tcl sector erasing eeeeh 5555h bnk bnk 2tcl read status 7777h nu nu nu 2tcl table 4 : code definition abbreviation definition s segment of the target flash memory cell addoff segment offset of the target flash memory cell which must be even an value (word-aligned address). w data (word) to be written in flash. dwl,dwh data (double word, dhl = low word, dwh = high word to be written in flash, begaddoff segment offset of the first target flash memory word to be written in a multiple programming com- mand. this value must be even (word-aligned address) endaddoff segment offset of the last target flash memory word to be written in a multiple programming command. must be even value (word-aligned address). the value d = (endaddoff - begaddoff) must be: 0 <= d < 16384 (ie. up to one page (16 kbytes) can be written in the flash with one multi-word program- ming command). sourceadd start address for the source data (block) to be programmed. this address uses implicitly the data paging mechanism of the cpu. sourceadd value must respect the rules: - sourceadd + (endaddoff - begaddoff) < 16384. - page 0 and 1 can not be used for source data if syscon bit roms1 = `1' note : source data can be located in flash (in pages 0, 1, 6, 7, 8, 9, 10 or 11 if bit roms1 = `0', or in pages 4, 5, 6, 7, 8, 9, 10 or 11 if bit roms1 = `1'. bnk number of the bank to be erased. note that for security, r2 and r3 must hold the same value. 2tcl cpu clock period in nseconds (e.g. r4 = 40d means cpu frequency is 25mhz). ST10F163 12/58 the flash unlock sequence consists of two con- secutive writes: the direct addressing mode and the indirect addressing mode. the fcr must rep- resent an even address in the active address space of the flash memory. rwn can be any unused word gpr (r6 to r15), loaded with a value that results in the same even address as for fcr for easier coding, the standard data paging addressing scheme is overridden for the two mov instruction of the flash trigger sequence (exts instruction). this also locked both standard and pec interrupts and class a hardware traps. must be replace by atomic instruction if standard dpp addressing scheme must be preserved. when the embedded programming/erasing algo- rithm returns to trigger point, information can be collected through register r0 so the user can take specific actions. table 5 lists all of the error codes that can be returned in r0. note the flash embedded presto algorithms require at least 45 words on the internal system stack for proper operation. the program verifies itself that there is enough free space on the system stack before performing a programming or erasing operation (by comparing sp value with stkov+90d). exts #1, #2 ; assumes flash is mapped in seg 1 mov fcr, r7 ; first part mov [r7], r7 ; second part table 5 : error code definition error code meaning 00h operation was successful 01h romen bit inside syscon is not set 02h vpp voltage not present 03h programming operation failed 04h address value (r1) incorrect: not in flash address area or odd 05h cpu period out of range (must be between 10 ns to 1000 ns) 06h not enough free space on system stack for proper operation 07h incorrect bank number (r2,r3) specified 08h erase operation failed 09h bad source address for multi-word programming command 0ah bad number of words to be copied in multi-word programming command: one destination will be out of flash, or one source operand will be out of the source page ffh unknown or bad command ST10F163 13/58 v.1.1 - return values after a single or double word programming com- mand, r0 contains error code, r1 remains unchanged, r2 will contain the data in flash for location segment+segment offset (r0.[3:0] with r1), r3 will contain the data in flash for location segment+segment offset +2 (r0[3:0] with r1+2), r4 to r15 remain unchanged. after a multi-word programming command, r0 contains error code, r1 will contains the last seg- ment offset address of the last written word in flash (failing flash address if r0 is not equal to zero), r2 and r3 are undefined, r4 to r15 remain unchanged. after erasing command, only r4 to r15 remain unchanged, r0 will contain error code, r1 to r3 are undefined. after status read command, r0 contains error code, r1 contains flash embedded revision, r2 and r3 contains circuit identifiers (r2 = #0787h and r3 = #0101h for this device), r4 to r15 remain unchanged. v.1.2 - programming examples programming a double word: note for easier coding, the standard data paging addressing scheme is overrides for the two mov instruction of the flash trigger sequence (exts instruction).this also locked both standard and pec interrupts and class a hardware traps. must be replace by atomic instruction if standard dpp addressing scheme must be preserved. programming a block of data: address 01'9000h to 01'9ffeh (inclusive) is to be programmed. source data (data to be copied into flash) is located in external ram from address 03'1000h (to 03'1ffeh, implicitly): ; code hereafter assumes that flash is mapped in segment 1 ; i.e. bit roms1 = `1' in syscon register ; flash must also be enabled, i.e. bit romen = `1' in syscon. mov r0, #progdw ; dd4xh: double word programming command or r0, #01h ; selects segment 1 in flash memory mov r1, #00224h ; address to be programmed is 01'0224h mov r2, #03456h ; data to be programmed at 01'0224h mov r3, #04567h ; data to be programmed at 01'0226h mov r4, #050d ; 50ns is 20 mhz cpu clock frequency mov r7, #08000h ; r7 used for flash trigger sequence #define fcr 08000h ; flash unlock sequence: consists in two consecutive writes, with the direct addressing mode and then the indirect addressing mode. fcr must represent an even address in the active address space of the flash memory, and rwn can be any unused word gpr (r6 to r15)loaded with a value resulting in the same even address than fcr exts #1, #2 ; flash can be mapped in segment 0 or 1 mov fcr, r7 ; first part mov [r7], r7 ; second part nop ; warning: place 2 nop operations after nop ; the unlock sequence to avoid all possible ; pipeline conflict in steak programs ; code hereafter assumes that flash is mapped in segment 1 ; i.e. bit roms1 = `1' in syscon register ; flash must also be enabled, i.e. bit romen = `1' in syscon. mov r0, #progmw ; aa5xh: multi word programming command or r0, #01h ; selects segment 1 in flash memory ST10F163 14/58 v.2 - flash memory configuration the default memory configuration is determined by the state of the ea pin at reset. this value is stored in the internal rom enable bit: romen of the syscon register. when romen=0, the internal rom is disabled and external rom is used for start-up control. the first 32kbytes of the flash memory area must be re-mapped to segment 1, to enable their later use. this is done by setting the roms1 bit of syscon to 0. this is done by the externally sup- plied program, before the execution of the einit instruction. if program execution starts from external memory, but access to the flash memory (re-mapped to bank 1) is required later, one of the following val- ues has to be written to the syscon register, before the end of initialization: if flash is to be mapped to segment 1: xxx100xxxxxxxxxxb (roms1=1,sgtdis=0) if flash is to be mapped to segment 0: xxx000xxxxxxxxxxb (roms1=0,sgtdis=0) all other parts of the flash memory (addresses 18000h - 1ffffh) remain unaffected. the sgtdis segmentation disable/enable must be set to 0 so that the 64kbytes of on-chip mem- ory can be used in addition to the external boot memory. the correct procedure for changing the segmentation registers must be observed, to pre- vent unwanted trap conditions: instructions that configure the internal memory must only be executed from external memory or from the internal ram. whenever the internal memory is disabled, ena- bled or re-mapped, the dpps must be explicitly (re)loaded to enable correct data accesses to the internal memory and/or external memory. v.3 - flash protection the flash protection mode, prevents the reading of data operands in the flash memory by anything but a program executed from the flash memory itself. flash protection mode permits program branches from, or into the flash memory, but does not permit erasing and programming of the flash memory. flash protection is controlled by the protection uprom programming bit (uprog). uprog is a 'hidden' one-time programmable bit. it is only accessible in a special mode, entered, for exam- ple, via a flash eprom programming board. if uprog is set to `1', flash protection is active after reset. by default flash protection is disabled (uprog=0). for deactivation of flash protection, where the flash memory has to be reprogrammed with updated program/variables, a zero value must be written at every even address in the active address space of the flash memory. this write can only be done by an instruction executed from the internal flash memory itself, e.g. mov flash,zeros. mov r1, #09000h ; first flash segment offset address mov r2, #09ffeh ; last flash segment offset address mov r3, #01000h ; source data address: use dpp2 as ; data page pointer scxt dpp2,#0ch ; source is in page 12 (0ch): save previous ; dpp2 value and load it with source page ; number mov r4, #050d ; 50ns is 20 mhz cpu clock frequency mov r7, #08000h ; r7 used for flash trigger sequence #define fcr 08000h exts #1, #2 ; flash can be mapped in segment 0 or 1 mov fcr, r7 ; first part mov [r7], r7 ; second part nop ; warning: place 2 nop operations after nop ; the unlock sequence to avoid all possible ; pipeline conflict in steak programs pop dpp2 ; restore dpp2 ST10F163 15/58 vi - external bus controller all of the external memory accesses are per- formed by a particular on-chip external bus con- troller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external mem- ory access modes: 16-/18-/20-/24-bit addresses, 16-bit data, de- multiplexed 16-/18-/20-/24-bit addresses, 16-bit data, multi- plexed 16-/18-/20-/24-bit addresses, 8-bit data, multi- plexed 16-/18-/20-/24-bit addresses, 8-bit data, de- multiplexed in the demultiplexed bus modes, addresses are output on port1 and data is input/output on port0 or p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input/output. important timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read write delay) have been made programmable. this gives the choice of a wide range of different types of memories and external peripherals. in addition, up to 4 independent address windows may be defined (via register pairs addrselx / bus- conx). this gives access to different resources with dif- ferent bus characteristics. these address win- dows are arranged hierarchically where buscon4 overrides buscon3 and buscon2 overrides buscon1. all accesses to locations not covered by these 4 address windows are controlled by buscon0. up to 5 external cs signals (4 windows plus default) can be generated in order to save external glue logic. access to very slow memories is sup- ported via a particular `ready' function. a hold/hlda protocol is available for bus arbi- tration so that external resources can be shared with other bus masters. the bus arbitration is enabled by setting bit hlden in register syscon. after setting hlden once, pins p6.7...p6.5 (breq, hlda, hold) are automati- cally controlled by the ebc. in master mode (default after reset) the hlda pin is an output. by setting bit dp6.7 to'1' the slave mode is selected where pin hlda is switched to input. this allows to directly connect the slave controller to another master controller without glue logic. for applications which require less than 16 mbytes of external memory space, this address space can be restricted to 1 mbyte, 256 kbyte or to 64 kbyte. in this case port 4 outputs four, two or no address lines at all. if an address space of 16 mbytes is used, it outputs all 8 address lines. note when the on-chip ssp module is to be used the segment address output on port 4 must be limi ted to 4 bits (i.e. a19...a16) in order to enable the alternate function of the ssp interface pins. vi.1 - programmable chip select timing control the position of the csx lines can be changed by setting the cscfg bit in the syscon register. by default the csx lines change half a cpu clock cycle after the rising edge of ale (20ns @ f cpu = 25 mhz). with the cscfg bit set (section figure vii - ), the csx lines change with the rising edge of ale. in this case, the csx lines and address lines change at the same time. ST10F163 16/58 figure 4 : chip select delay delay normal csx rd address (p1) ale segment (p4) normal demultiplexed bus cycle ale lengthen demultiplexed bus cycle unlatched csx wr data data data bus (p0) bus (p0) read/write delay read/write data ST10F163 17/58 vii - central processing unit (cpu) the main core of the cpu consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedicated sfrs. additional hard- ware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. based on these hardware provisions, most of the ST10F163's instructions can be executed in one machine cycle. this requires 80ns at 25mhz cpu clock. for example, shift and rotate instructions are always processed in one machine cycle inde- pendent of the number of bits to be shifted. all multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 x 16 bit mul- tiplication in 5 cycles and a 32-/16 bit division in 10 cycles. the `jump cache' pipeline optimiza- tion, reduces the execution time of repeatedly per- formed jumps in a loop, from 2 cycles to 1 cycle. the cpu includes an actual register context. this consists of up to 16 wordwide gprs physically allocated in the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, one register bank may overlap others. a system stack of up to 1024 bytes is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate address- ing modes exist. figure 5 : cpu block diagram 16 16 32 rom internal ram 1kbyte r15 r0 general purpose registers r0 r15 mdh mld barrel-shift mul./div.-hw bit-mask gen. alu 16-bit context ptr sp stkov stkun exec. unit instr. ptr instr. reg 4-stage pipeline psw syscon buscon 0 buscon 1 buscon 2 buscon 3 buscon 4 addrsel 1 addrsel 2 addrsel 3 addrsel 4 data pg. ptrs code seg. ptr. cpu 128kbytes flash ST10F163 18/58 viii - interrupt system with an interrupt response time from 200 ns to 480ns (in the case of internal program execution), the ST10F163 reacts quickly to the occurrence of non-deterministic events. the architecture of the ST10F163 supports sev- eral mechanisms for fast and flexible response to service requests that can be generated from vari- ous sources internal or external to the microcon- troller. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in a standard interrupt service, program execution is suspended and a branch to the inter- rupt vector table is performed. for a pec service, just one cycle is `stolen' from the current cpu activity. a pec service is a single byte or word data transfer between any two memory locations with an additional increment of either the pec source or the destination pointer. an individual pec transfer counter is decremented for each pec service, except for the continuous transfer mode. when this counter reaches zero, a stan- dard interrupt is performed to the corresponding source related vector location. pec services are suited to, for example, the transmission or recep- tion of blocks of data. the ST10F163 has 8 pec channels, each of which offers fast inter- rupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. via its related register, each source can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedi- cated vector location. fast external interrupt inputs are provided to ser- vice external interrupts with high precision requirements. these fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the `trap' instruction in combination with an individ- ual trap (interrupt) number. table 6 shows all of the possible ST10F163 inter- rupt sources and the corresponding hard- ware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: table 6 : list of possible interrupt sources, flags, vector and trap numbers source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number external interrupt 0 cc8ir cc8ie cc8int 00'0060h 18h external interrupt 1 cc9ir cc9ie cc9int 00'0064h 19h external interrupt 2 cc10ir cc10ie cc10int 00'0068h 1ah external interrupt 3 cc11ir cc11ie cc11int 00'006ch 1bh external interrupt 4 cc12ir cc12ie cc12int 00'0070h 1ch external interrupt 5 cc13ir cc13ie cc13int 00'0074h 1dh external interrupt 6 cc14ir cc14ie cc14int 00'0078h 1eh external interrupt 7 cc15ir cc15ie cc15int 00'007ch 1fh gpt1 timer 2 t2ir t2ie t2int 00'0088h 22h gpt1 timer 3 t3ir t3ie t3int 00'008ch 23h gpt1 timer 4 t4ir t4ie t4int 00'0090h 24h gpt2 timer 5 t5ir t5ie t5int 00'0094h 25h gpt2 timer 6 t6ir t6ie t6int 00'0098h 26h gpt2 caprel register crir crie crint 00'009ch 27h asc0 transmit s0tir s0tie s0tint 00'00a8h 2ah asc0 transmit buffer s0tbir s0tbie s0tbint 00'011ch 47h asc0 receive s0rir s0rie s0rint 00'00ach 2bh asc0 error s0eir s0eie s0eint 00'00b0h 2ch ST10F163 19/58 the ST10F163 provides an excellent mechanism to identify and to process exceptions or error con- ditions that arise during run-time, called`hardware traps'. hardware traps cause an immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedi- cated vector table location). the occurrence of a hardware trap is additionally signified by an indi- vidual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap ser- vices can normally not be interrupted by standard or pec interrupts. table 7 shows all of the possible exceptions or error conditions that can arise during run time. ssp interrupt xp1ir xp1ie xp1int 00'0104h 41h pll unlock / owd xp3ir xp3ie xp3int 00'010ch 43h table 6 : list of possible interrupt sources, flags, vector and trap numbers (continued) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number table 7 : exceptions or error conditions that can arise during run-time exception conditio n trap flag trap vector vector location trap number trap priority reset functions: hardware reset reset 00'0000h 00h iii software reset reset 00'0000h 00h iii watchdog timer overflow reset 00'0000h 00h iii class a hardware traps: non-maskable interrupt nmi nmitrap 00'0008h 02h ii stack overflow stkof stotrap 00'0010h 04h ii stack underflow stkuf stutrap 00'0018h 06h ii class b hardware traps: undefined opcode undopc btrap 00'0028h 0ah i protected instruction fault prtflt btrap 00'0028h 0ah i illegal word operand access illopa btrap 00'0028h 0ah i illegal instruction access illina btrap 00'0028h 0ah i illegal external bus access illbus btrap 00'0028h 0ah i reserved [2ch 3ch] [0bh 0fh] software traps: trap instruction any [00'0000h 00'01fch] in steps of 4h any [00h 7fh] current cpu priority ST10F163 20/58 ix - general purpose timer (gpt) unit the gpt unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse gener- ation, or pulse multiplication. the gpt unit con- tains five 16-bit timers organized into two separate modules gpt1 and gpt2. each timer in each module may operate independently in several dif- ferent modes, or may be concatenated with another timer of the same module. ix.1 - gpt1 each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of three basic modes of operation: timer , gated timer , and counter mode. in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable pre-scaler. in counter mode a timer is clocked in reference to external events. gated timer mode supports pulse width or duty cycle measurement, where the oper- ation of a timer is controlled by the `gate' level on an external input pin. each timer has one associ- ated port pin (txin) which serves as gate or clock input. table 8 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 mhz cpu clock (see table 8). the count direction (up/down) for each timer is programmable by software or is altered dynami- cally by an external signal on a port pin (txeud). for example, this facilitates position tracking. timer t3 has output toggle latches (txotl) which changes state on each timer over-flow/underflow. the state of this latch may be output on port pins (txout) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as reload or capture registers, timers t2 and t4 are stopped. the content of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the con- tents of t2 or t4, triggered, either by an external signal or by a selectable state transition of its tog- gle latch, t3otl. when both t2 and t4 are con- figured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention. ix.2 - gpt2 the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programma- ble by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is sup- ported via the output toggle latch (t6otl) of timer t6 which changes its state on each timer over- flow/underflow. the state of this latch may be used to clock timer t5, or it may be output on a port pin (t6out). the overflows/underflows of timer t6 can additionally be used to clock the capcom timers t0 or t1, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture proce- dure. this allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. table 9 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 mhz cpu clock. table 8 : gpt1 timer input frequencies, resolution and periods f cpu = 25mhz timer inpu t selection t2i / t3i / t4i 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b pre-scaler factor 8 16 32 64 128 256 512 1024 input frequency 3.125mhz 1.563mhz 781.3khz 390.6khz 195.3khz 97.66khz 48.83khz 24.41khz resolution 320 ns 640 ns 128 ns 2.56 m s 5.12 m s 10.24 m s 20.48 m s 40.96 m s period 21.0 ms 41.9 ms 83.9 ms 167 ms 336 ms 671 ms 1.34 s 2.68 s ST10F163 21/58 table 9 : gpt2 timer input frequencies, resolution and period f cpu = 25mhz timer input selection t5i / t6i 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b pre-scaler factor 4 8 16 32 64 128 256 512 input frequency 6.25mhz 3.125mhz 1.563mhz 781.3khz 390.6khz 195.3khz 97.66khz 48.83khz resolution 160ns 320 ns 640 ns 128 ns 2.56 m s 5.12 m s 10.24 m s 20.48 m s period 10.49ms 21.0 ms 41.9 ms 83.9 ms 167 ms 336 ms 671 ms 1.34 s figure 6 : block diagram of gpt1 2 n n=3...10 2 n n=3...10 2 n n=3...10 t2eud t2in cpu clock cpu clock cpu clock t3in t4in t3eud t4eud t2 mode control t3 mode control t4 mode control gpt1 timer t2 gpt1 timer t3 gpt1 timer t4 t3otl reload capture u/d u/d reload capture interrupt request interrupt request interrupt request t3out u/d ST10F163 22/58 figure 7 : block diagram of gpt2 2 n n=2...9 2 n n=2...9 t5eud t5in cpu clock cpu clock t6in t6eud t5 mode control t6 mode control gpt2 timer t5 gpt2 timer t6 u/d interrupt request u/d gpt2 caprel t60tl toggle ff t6out capin reload interrupt request capture clear interrupt request ST10F163 23/58 x - parallel ports the ST10F163 provides up to 77 i/o lines which are organized into six input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) pro- grammable as, either inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of three i/ o ports can be configured (pin by pin) for push/pull operation or open-drain operation via control regis- ters. during the internal reset, all port pins are con- figured as inputs. all port lines have associated, programmable, alternate input or output functions. port0 and port1 may be used as address and data lines when accessing external memory. port 4 outputs the additional segment address bits a23/ 19/17...a16 in systems where segmentation is enabled to access more than 64 kbytes of mem- ory. port 6 provides optional bus arbitration signals (breq, hlda, hold) and chip select signals. port 3 includes alternate functions of timers, serial inter- faces, the optional bus control signal bhe and the system clock output (clkout). port 5 is used for timer control signals. all port lines that are not used for these alternate functions may be used as gen- eral purpose i/o lines. xi - serial channels serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces, an asynchronous/synchronous serial channel (asc0) and a synchronous serial port (ssp). asc0 : the table below shows the baud rates for the asynchronous/synchronous serial channel. a dedicated baud rate generator is used to set up all standard baud rates without oscillator tuning. 3 separate interrupt vectors are provided for trans- mission, reception, and erroneous reception. in asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. for multi- processor communication, a mechanism to distin- guish address from data bytes has been included (8-bit data + wake up bit mode). in synchronous mode, the asc0 transmits or receives bytes (8 bits) synchronously to a shift clock which is gener- ated by the asc0. the asc0 always shifts the lsb first. a loop back option is available for testing purposes. a number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. a parity bit can automatically be generated on transmis- sion or be checked on reception. framing error detection allows to recognize data frames with missing stop bits. an overrun error will be gener- ated, if the last character received has not been read out of the receive buffer register by the time the reception of a new character is complete. note the deviation errors given in the table above are rounded. using a baudrate crystal will provide correct baudrates without deviation errors. table 10 : commonly used baud rates by reload value and deviation errors s0brs = `0', f cpu = 25mhz s0brs = `1', f cpu = 25mhz baud rate (baud) deviation error reload value baud rate (baud) deviation error reload value 781250 0.0% 0000 h 520833 0.0% 0000 h 56000 +7.3% /-0.4% 000c h / 000d h 56000 +3.3% / -7.0% 0008h / 0009h 38400 +1.7% / -3.1% 0013 h / 0014 h 38400 +4.3% / -3.1% 000ch / 000dh 19200 +1.7% / -0.8% 0027 h / 0028 h 19200 +0.5% / -3.1% 001ah / 001bh 9600 +0.5% / -0.8% 0050 h / 0051 h 9600 +0.5% / -1.4% 0035h / 0036h 4800 +0.5% / -0.1% 00a1 h / 00a2 h 4800 +0.5% / -0.5% 006bh / 006ch 2400 +0.2% / -0.1% 0144 h / 0145 h 2400 +0.0% / -0.5% 00d8h / 00d9h 1200 +0.0% / -0.1% 028a h / 028b h 1200 +0.0% / -0.2% 01b1h / 01b2h 600 +0.0% / -0.1% 0515 h / 0516 h 600 +0.0% / -0.1% 0363h / 0364h 95 +0.4% / 0.4% 1fff h / 1fff h 75 +0.0% / 0.0% 1b1fh / 1b20h 63 +0.9% / 0.9% 1fffh / 1fffh ST10F163 24/58 ssp: the synchronous serial port provides high-speed serial communication with external slave devices such as eeprom. the ssp trans- mits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift clock which is generated by the ssp. the ssp can start shifting with the lsb or with the msb and is used to select shifting and latching clock edges as well as the clock polarity. up to two chip select lines may be activated in order to direct data transfers to one or both of two peripheral devices. table 11 : synchronous baud rate and sspcks reload values sspcks value synchronous baud rate 000 ssp clock = cpu clock divided by 2 12.5 mbit/s 001 ssp clock = cpu clock divided by 4 6.25 mbit/s 010 ssp clock = cpu clock divided by 8 3.13 mbit/s 011 ssp clock = cpu clock divided by 16 1.56 mbit/s 100 ssp clock = cpu clock divided by 32 781 kbit/s 101 ssp clock = cpu clock divided by 64 391 kbit/s 110 ssp clock = cpu clock divided by 128 195 kbit/s 111 ssp clock = cpu clock divided by 256 97.7 kbit/s ST10F163 25/58 xii - watchdog timer the watchdog timer is a fail-safe mechanism which the maximum malfunction time of the con- troller the watchdog timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. in this way the chip's start-up procedure is always monitored. the software must be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset and pulls the rstout pin low in order to allow external hardware components to be reset. the watchdog timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. the high byte of the watchdog timer register can be set to a pre-specified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is ser- viced by the application software, the high byte of the watchdog timer is reloaded. the table 12 shows the watchdog time range which for a 25mhz cpu clock. some numbers are rounded to 3 significant digits. xiii - oscillator watchdog (owd) the oscillator watchdog (owd) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). for this operation the pll provides a clock signal to supervise transitions on the oscillator clock. this pll clock is independent from the xtal1 clock. when the expected oscillator clock transi- tions are missing, the owd activates the pll unlock/owd interrupt node and supplies the cpu with the pll clock signal. under these circum- stances the pll will oscillate with its basic fre- quency. a low level on pin owe disables the owd's inter- rupt output, so that the clock signal is derived from the oscillator clock. the cpu clock source is only switched back to the oscillator clock after a hard- ware reset. when the direct-drive, or direct-drive-with- pres- caler clock option is selected, an oscillator watch- dog is implemented. this provides a fail-safe mechanism in the case of a loss of external clock. after reset, the oscillator watchdog is enabled by default. to disable the owd, the bit owddis (bit 4 of syscon register) must be set. when the owd is enabled, pll runs on free-running fre- quency, and increments the oscillator watchdog counter. on each transition of xtal1 pin, the oscillator watchdog is cleared. if an external clock failure occurs, then the oscillator watchdog counter overflows (after 16 pll clock cycles). the cpu clock signal is switched to the pll free-run- ning clock signal, and the oscillator watchdog interrupt request (xp3int) is flagged. the cpu clock will not switch back to the external clock even if a valid external clock exits on xtal1 pin. only a hardware reset can switch the cpu clock source back to direct clock input. when the owd is disabled, the cpu clock is always fed from the oscillator input and the pll is switched off to decrease power supply current. note for security, rewrite wdtcon each time before the watchdog timer is serviced. table 12 : watchdog time range for 25mhz cpu clock reload value in wdtrel prescaler for f cpu 2 (wdtin = `0') 128 (wdtin = `1') ff h 20.48 m s 1.31 ms 00 h 5.24 ms 336 ms ST10F163 26/58 xiv - instruction set summary the table below lists the instruction set of the ST10F163. more detailed information such as address modes, instruction operation, parameters for con- ditional execution of instructions, opcodes and a detailed description of each instruction can be found in the ast10 family programming man- ualo table 13 : instruction set mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand. with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 ST10F163 27/58 calla, calli, callr call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from sys- tem stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi-pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 13 : instruction set (continued) mnemonic description bytes ST10F163 28/58 xv - special function register overview the following table lists sfrs in alphabetical order. bit-addressable sfrs are marked with the letter abo in column anameo. sfrs within the extended sfr-space (esfrs) are marked with the letter aeo in column aphysical addresso. regis- ters with on-chip x-peripherals (can) are marked with the letter axo in column physical address. an sfr can be specified by its individual mne- monic name. depending on the selected addressing mode, an sfr can be accessed via its physical address (using the data page pointers), or via its short 8-bit address (without using the data page point- ers). table 14 : special function register list name physical address 8-bit address description reset value addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h buscon0 b ff0ch 86h bus configuration register 0 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h caprel fe4ah 25h gpt2 capture/reload register 0000h cc8ic b ff88h c4h ex0in interrupt control register 0000h cc9ic b ff8ah c5h ex1in interrupt control register 0000h cc10ic b ff8ch c6h ex2in interrupt control register 0000h cc11ic b ff8eh c7h ex3in interrupt control register 0000h cc12ic b ff90h c8h ex4in interrupt control register 0000h cc13ic b ff92h c9h ex5in interrupt control register 0000h cc14ic b ff94h cah ex6in interrupt control register 0000h cc15ic b ff96h cbh ex7in interrupt control register 0000h cp fe10h 08h cpu context pointer register fc00h cric b ff6ah b5h gpt2 caprel interrupt control register 0000h csp fe08h 04h cpu code segment pointer register (read only) 0000h dp0l b f100h e 80h p0l direction control register 00h dp0h b f102h e 81h p0h direction control register 00h dp1l b f104h e 82h p1l direction control register 00h dp1h b f106h e 83h p1h direction control register 00h dp2 b ffc2h e1h port 2 direction control register 0000h dp3 b ffc6h e3h port 3 direction control register 0000h dp4 b ffcah e5h port 4 direction control register 00h dp6 b ffceh e7h port 6 direction control register 00h dpp0 fe00h 00h cpu data page pointer 0 register (10 bits) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10 bits) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10 bits) 0002h ST10F163 29/58 dpp3 fe06h 03h cpu data page pointer 3 register (10 bits) 0003h exicon b b f1c0h e e0h external interrupt control register 0000h idchip f07ch e 3eh device identifier register 0a3xh 1) idmanuf f07eh e 3fh manufacturer identifier register 0400h idmem f07ah e 3dh on-chip memory identifier register 3020h idprog f078h e 3ch programming voltage identifier register 9a40h mdc b ff0eh 87h cpu multiply divide control register 0000h mdh fe0ch 06h cpu multiply divide register high word 0000h mdl fe0eh 07h cpu multiply divide register low word 0000h odp2 b f1c2h e e1h port 2 open drain control register 0000h odp3 b f1c6h e e3h port 3 open drain control register 0000h odp6 b f1ceh e e7h port 6 open drain control register 00h ones ff1eh 8fh constant value 1's register (read only) ffffh p0l b ff00h 80h port 0 low register (lower half of port0) 00h p0h b ff02h 81h port 0 high register (upper half of port0) 00h p1l b ff04h 82h port 1 low register (lower half of port1) 00h p1h b ff06h 83h port 1 high register (upper half of port1) 00h p2 b ffc0h e0h port 2 register 0000h p3 b ffc4h e2h port 3 register 0000h p4 b ffc8h e4h port 4 register (8 bits) 00h p5 b ffa2h d1h port 5 register (read only) xxxxh p6 b ffcch e6h port 6 register (8 bits) 00h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h psw b ff10h 88h cpu program status word 0000h rp0h b f108h e 84h system start-up configuration register (rd. only) xxh s0bg feb4h 5ah serial channel 0 baud rate generator reload reg 0000h s0con b ffb0h d8h serial channel 0 control register 0000h s0eic b ff70h b8h serial channel 0 error interrupt control register 0000h s0rbuf feb2h 59h serial channel 0 receive buffer register (read only) xxh s0ric b ff6eh b7h serial channel 0 receive interrupt control register 0000h table 14 : special function register list (continued) name physical address 8-bit address description reset value ST10F163 30/58 s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control reg 0000h s0tbuf feb0h 58h serial channel 0 transmit buffer register (write only) 00h s0tic b ff6ch b6h serial channel 0 transmit interrupt control register 0000h sp fe12h 09h cpu system stack pointer register fc00h sspcon0 ef00h x --- ssp control register 0 0000h sspcon1 ef02h x --- ssp control register 1 0000h ssprtb ef04h x --- ssp receive/transmit buffer xxxxh ssptbh ef06h x --- ssp transmit buffer high xxxxh stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h syscon b ff12h 89h cpu system configuration register 0xx0h 2) t2 fe40h 20h gpt1 timer 2 register 0000h t2con b ff40h a0h gpt1 timer 2 control register 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register 0000h t3 fe42h 21h gpt1 timer 3 register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t3ic b ff62h b1h gpt1 timer 3 interrupt control register 0000h t4 fe44h 22h gpt1 timer 4 register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t4ic b ff64h b2h gpt1 timer 4 interrupt control register 0000h t5 fe46h 23h gpt2 timer 5 register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t5ic b ff66h b3h gpt2 timer 5 interrupt control register 0000h t6 fe48h 24h gpt2 timer 6 register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t6ic b ff68h b4h gpt2 timer 6 interrupt control register 0000h tfr b ffach d6h trap flag register 0000h wdt feaeh 57h watchdog timer register (read only) 0000h wdtcon ffaeh d7h watchdog timer control register 000xh 3) xp1ic b f18eh e c7h ssp interrupt control register 0000h xp3ic b f19eh e cfh pll unlock interrupt control register 0000h zeros b ff1ch 8eh constant value 0's register (read only) 0000h 1. the value depends on the silicon revision and is given in the errata sheet. 2. the system configuration is selected during reset. 3. bit wdtr indicates a watchdog timer triggered reset. table 14 : special function register list (continued) name physical address 8-bit address description reset value ST10F163 31/58 xvi - electrical characteristics xvi.1 - absolute maximum ratings ambient temperature under bias ( t a ): 0 to +70 c storage temperature ( t st ): 65 to +150 c voltage on v dd pins with respect to ground ( v ss ): 0.5 to +6.5 v voltage on any pin with respect to ground ( v ss ): 0.5 to v dd +0.5 v input current on any pin during overload condi- tion: 10 to +10 ma absolute sum of all input currents during over- load condition:|100 ma| power dissipation:1.5 w note stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in ST10F163 33/58 xvi.4 - ac characteristics xvi.4.1 - test waveforms figure 8 : supply/idle current as a function of operating frequency i [ma] f cpu [mhz] 5 10 15 20 100 50 10 i idmax i ccmax 25 figure 9 : input/output waveforms figure 10 : float waveforms 2.4v 0.45v test points 0.2v dd +0.9 0.2v dd +0.9 0.2v dd -0.1 0.2v dd -0.1 ac inputs during testing are driven at 2.4 v for a logic `1' and 0.4 v for a logic `0'. timing measurements are made at vih min for a logic `1' and vil max for a logic `0'. for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh /v ol level occurs (i oh /i ol = 20 ma). timing reference points v load +0.1v v load -0.1v v oh -0.1v v ol +0.1v v load v ol v oh ST10F163 34/58 xvi.4.2 - definition of internal timing the internal operation of the ST10F163 is con- trolled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipe- line) or external (e.g. bus cycles) operations. the specification of the external timing (ac char- acteristics) therefore depends on the time between two consecutive edges of the cpu clock, called atclo (see figure below). the cpu clock signal can be generated by differ- ent mechanisms. the duration of tcls and their variation (and also the derived external timing) depends on the used mechanism to generate f cpu . this influence must be regarded when cal- culating the timings for the ST10F163. the example for pll operation shown in the fig- ure above refers to a pll factor of 4. the mecha- nism used to generate the cpu clock is selected during reset by the logic levels on pins p0.15-13 (p0h.7-5). xvi.4.3 - clock generation modes the table below associates the combinations of these three bits with the respective clock generation mode. figure 11 : generation mechanisms for the cpu clock p0.15-13 (p0h.7-5) cpu frequency f cpu =f xtal *f external clock input range 1) 1. the external clock input range refers to a cpu clock range of 1...25 mhz. notes 111 f xtal * 4 2.5 to 6.25 mhz default configuration 110 f xtal * 3 3.33 to 8.33 mhz 101 f xtal *2 5to12.5mhz 100 f xtal * 5 2 to 5 mhz 011 f xtal * 1 1 to 25 mhz direct drive 2) 2. the maximum depends on the duty cycle of the external clock signal. 010 f xtal * 1.5 6.66 to 16.6 mhz 001 f xtal / 2 2 to 50 mhz cpu clock via prescaler 3) 3. the maximum input frequency is 25 mhz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40 w . however, higher frequency can be applied with an external clock source, but in this case, the input clock signal must reach the defined levels v il and v ih2. 000 f xtal * 2.5 4 to 10 mhz tcltcl f cpu f xtal f cpu f xtal phase locked loop operation direct clock drive tcl tcl f cpu f xtal prescaler operation tcltcl ST10F163 35/58 xvi.4.4 - prescaler operation when pins p0.15-13 (p0h.7-5) equal '001' during reset, the cpu clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f xtal and the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the period of the input clock f xtal . the timings listed in the ac characteristics that refer to tcls therefore can be calculated using the period of f xtal for any tcl. note that if the bit owddis in syscon register is cleared, the pll is running on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. xvi.4.5 - direct drive when pins p0.15-13 (p0h.7-5) equal'011' during reset the on-chip phase locked loop is disabled and the cpu clock is directly driven from the inter- nal oscillator with the input clock signal. the frequency of f cpu directly follows the fre- quency of f xtal so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . the timings listed below that refer to tcls there- fore must be calculated using the minimum tcl that is possible under the respective circum- stances. this minimum value can be calculated by the following formula: for two consecutive tcls the deviation caused by the duty cycle of f xtal is compensated so the duration of 2tcl is always 1/f xtal . the minimum value tcl min therefore has to be used only once for timings that require an odd number of tcls (1,3,...). timings that require an even number of tcls (2,4,...) may use the formula: note the address float timings in multiplexed bus mode (t 11 and t 45 ) use the maximum duration of tcl (tcl max = 1/f xtal * dc max ) instead of tcl min . if bit owddis in the syscon register is cleared, the pll runs on its free-running frequency and delivers the clock signal for the oscillator watch- dog. if bit owddis is set, then the pll is switched off. xvi.4.6 - oscillator watchdog (owd) when the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the pll circuitry. this oscillator watchdog operates as follows: after a reset, the oscillator watchdog is enabled by default. to disable the owd, the bit owddis (bit 4 of syscon register) must be set. when the owd is enabled, the pll is running on its free-running frequency, and increment the oscillator watchdog counter. on each transition of xtal1 pin, the oscillator watchdog is cleared. if an external clock failure occurs, then the oscillator watchdog counter overflows (after 16 pll clock cycles). the cpu clock signal will be switched to the pll free-running clock signal, and the oscilla- tor watchdog interrupt request (xp3int) is flagged. the cpu clock will not switch back to the external clock even if a valid external clock exits on xtal1 pin. only a hardware reset can switch the cpu clock source back to direct clock input. when the owd is disabled, the cpu clock is always fed from the oscillator input and the pll is switched off to decrease power supply current. xvi.4.7 - phase locked loop for all other combinations of pins p0.15-13 (p0h.7-5) during reset the on-chip phase locked loop is enabled and provides the cpu clock (see table above). the pll multiplies the input fre- quency by the factor f which is selected via the combination of pins p0.15-13 (i.e. f cpu =f xtal * f). with every f'th transition of f xtal the pll cir- cuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. due to this adaptation to the input clock the fre- quency of f cpu is constantly adjusted so it is locked to f xtal . the slight variation causes a jitter of f cpu which also effects the duration of individ- ual tcls. the timings listed in the ac characteristics that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. tcl min 1f M xtal *dc min = dc duty cycle = 2 tcl 1 f xtal M = ST10F163 36/58 the actual minimum value for tcl depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one tcl is lower than for one single tcl (see formula and figure below). for a period of n * tcl the minimum value is computed using the corresponding deviation d n : where n = number of consecutive tcls and 1 n 40. so for a period of 3 tcls (n = 3): this is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or mea- surement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible (see figure 12). xvi.4.8 - memory cycle variables the tables below use three variables which are derived from the busconx registers and repre- sent the special characteristics of the pro- grammed memory cycle. the following table describes, how these variables are to be com- puted. tcl min tcl nom *1 l d n l 100 M ) ( = d n 4 n 15 ) % [] M ( = d 3 4315 M = 3.8% = 3tcl min 3tcl nom 1 3.8 100 M () = tcl nom 0.962 = 57.72nsec@f cpu 25mhz = () description symbol values ale extension t a tcl * ST10F163 37/58 xvi.4.9 - external clock drive xtal1 v dd =5v 10% v ss =0v t a = 0 to +70 c parameter symbol f cpu =f xtal f cpu =f xtal /2 f cpu =f xtal *n n = 1.5/2,/2.5/3/4/5 unit min max min max min max oscillator period t osc sr 40 1) 1000 20 500 40 * n 100 * n ns high time t 1 sr 18 2) 6 2) 10 2) ns low time t 2 sr 18 2) 6 2) 10 2) ns rise time t 3 sr 10 2) 6 3) 10 2) ns fall time t 4 sr 10 2) 6 2) 10 2) ns 1. theoretical minimum. the real minimum value depends on the duty cycle of the input clock signal. 2. the input clock signal must reach the defined levels vil and vih2. figure 13 : external clock drive xtal1 t 1 t 3 t 4 v il t 2 t osc v ih2 ST10F163 38/58 xvi.4.10 - multiplexed bus v dd =5v 10% v ss =0v t a = 0 to +70 cc l = 100 pf ale cycle time = 6 tcl + 2t a +t c +t f (120 ns at 25-mhz cpu clock without waitstates) table 16 : multiplexed bus characteristics parameter symbol max. cpu clock 25 mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. ale high time t 5 cc 10 + t a tcl - 10 +t a ns address setup to ale t 6 cc 4 + t a tcl - 16+ t a ns address hold after ale t 7 cc 10 + t a tcl - 10 +t a ns ale falling edge to rd, wr (with rw-delay) t 8 cc 10 + t a tcl - 10 +t a ns ale falling edge to rd, wr (no rw-delay) t 9 cc -10 + t a -10 + t a ns address float after rd, wr (with rw-delay) t 10 cc66ns address float after rd, wr (no rw-delay) t 11 cc 26 tcl + 6 ns rd, wr low time (with rw-delay) t 12 cc 30 + t c 2tcl - 10 +t c ns rd, wr low time (no rw-delay) t 13 cc 50 + t c 3tcl - 10 +t c ns rd to valid data in (with rw-delay) t 14 sr 20 + t c 2tcl - 20 +t c ns rd to valid data in (no rw-delay) t 15 sr 40 + t c 3tcl - 20 +t c ns ale low to valid data in t 16 sr 40 +t a +t c 3tcl - 20 +t a +t c ns address/unlatched cs to valid data in t 17 sr 50 +2t a + t c 4tcl - 30 +2t a +t c ns data hold after rd rising edge t 18 sr00ns data float after rd t 19 sr 26 + t f 2tcl - 14 +t f ns data valid to wr t 22 cc 20 + t c 2tcl - 20 +t c ns data hold after wr t 23 cc 26 + t f 2tcl - 14 +t f ns ale rising edge after rd, wr t 25 cc 26 + t f 2tcl - 14 +t f ns address/unlatched cs hold after rd, wr t 27 cc 26 + t f 2tcl - 14 +t f ns ST10F163 39/58 ale falling edge to latched cs t 38 cc -4 - t a 10 - t a -4 - t a 10 - t a ns latched cs low to valid data in t 39 sr 40 + t c + 2t a 3tcl - 20 +t c +2t a ns latched cs hold after rd, wr t 40 cc 46 + t f 3tcl - 14 +t f ns ale fall. edge to rdcs, wrcs (with rw delay) t 42 cc 16 + t a tcl - 4 + t a ns ale fall. edge to rdcs, wrcs (no rw delay) t 43 cc -4 + t a -4+t a ns address float after rdcs, wrcs (with rw delay) t 44 cc00ns address float after rdcs, wrcs (no rw delay) t 45 cc 20 tcl ns rdcs to valid data in (with rw delay) t 46 sr 16 + t c 2tcl - 24 +t c ns rdcs to valid data in (no rw delay) t 47 sr 36 + t c 3tcl - 24 +t c ns rdcs, wrcs low time (with rw delay) t 48 cc 30 + t c 2tcl - 10 +t c ns rdcs, wrcs low time (no rw delay) t 49 cc 50 + t c 3tcl - 10 +t c ns data valid to wrcs t 50 cc 26 + t c 2tcl- 14+ t c ns data hold after rdcs t 51 sr00ns data float after rdcs t 52 sr 20 + t f 2tcl - 20 +t f ns address hold after rdcs, wrcs t 54 cc 20 + t f 2tcl - 20 +t f ns data hold after wrcs t 56 cc 20 + t f 2tcl - 20 +t f ns table 16 : multiplexed bus characteristics (continued) parameter symbol max. cpu clock 25 mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. ST10F163 40/58 figure 14 : external memory cycle: multiplexed bus, with/without read/write delay, normal ale data in data out address address t 38 t 10 ale csx bus p0 read cycle rd bus p0 write cycle wr, wrl, wrh t 5 t 16 t 39 t 40 t 25 t 27 t 18 t 14 t 22 t 23 t 12 t 8 t 8 t 6m t 19 clkout address a23-a16 (a15-a8) bhe t 17 t 6 t 7 t 9 t 11 t 13 t 15 t 16 t 12 t 13 address t 9 t 17 t 6 t 27 ST10F163 41/58 figure 15 : external memory cycle: multiplexed bus, with/without read/write delay, extended ale data out address data in address address ale rd write cycle wr wrl, wrh t 5 t 16 t 6 t 7 t 39 t 40 t 14 t 8 t 18 t 23 t 6 read cycle t 27 bus p0 bus p0 t 38 t 10 t 19 csx clkout t 25 t 17 t 9 t 11 t 15 t 12 t 13 t 8 t 10 t 9 t 11 t 12 t 13 t 22 a23-a16 (a15-a8) bhe t 27 t 17 t 6 ST10F163 42/58 figure 16 : external memory cycle: multiplexed bus, with/without read/write delay, normal ale, read/ write chip select data in data out address address t 44 ale bus p0 read cycle rdcsx bus p0 write cycle wrcsx t 5 t 16 t 25 t 27 t 51 t 46 t 50 t 56 t 48 t 42 t 42 t 6 t 52 clkout address a23-a16 (a15-a8) bhe t 17 t 6 t 7 t 43 t 45 t 49 t 47 t 16 t 48 t 49 address t 43 ST10F163 43/58 figure 17 : external memory cycle: multiplexed bus, with/without read/write delay, extended ale, read/ write chip select data out address data in address address ale rdcsx write cycle wr wrl, wrh t 5 t 16 t 6 t 7 t 46 t 42 t 42 t 50 t 18 t 56 t 6 read cycle t 54 bus p0 bus p0 t 44 t 19 a23-a16 (a15-a8) bhe clkout t 25 t 17 t 43 t 45 t 47 t 48 t 49 t 49 t 43 t 48 t 44 t 45 ST10F163 44/58 xvi.4.11 - demultiplexed bus v dd =5v 10% v ss =0v t a = 0 to +70 cc l = 100 pf ale cycle time = 4 tcl + 2t a +t c +t f (80 ns at 25 mhz cpu clock without waitstates) table 17 : demultiplexed bus characteristics parameter symbol max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. ale high time t 5 cc 10 + t a tcl - 10+ t a ns address setup to ale t 6 cc 4 + t a tcl - 16+ t a ns address/unlatched cs setup to rd, wr (with rw-delay) t 80 cc 30 + 2t a 2tcl - 10 +2t a ns address/unlatched cs setup to rd, wr (no rw-delay) t 81 cc 10 + 2t a tcl -10 +2t a ns rd, wr low time (with rw-delay) t 12 cc 30 + t c 2tcl - 10 +t c ns rd, wr low time (no rw-delay) t 13 cc 50 + t c 3tcl - 10 +t c ns rd to valid data in (with rw-delay) t 14 sr 20 + t c 2tcl - 20 +t c ns rd to valid data in (no rw-delay) t 15 sr 40 + t c 3tcl - 20 +t c ns ale low to valid data in t 16 sr 40 + t a + t c 3tcl - 20 +t a +t c ns address/unlatched cs to valid data in t 17 sr 50 + 2t a + t c 4tcl - 30 +2t a +t c ns data hold after rd rising edge t 18 sr00ns data float after rd rising edge (with rw-delay 1) ) t 20 sr 26 + t f 2tcl - 14 +t f + 2t a 1) ns data float after rd rising edge (no rw-delay 1) ) t 21 sr 10 + t f tcl - 10 +t f + 2t a 1) ns data valid to wr t 22 cc 20 + t c 2tcl- 20 +t c ns data hold after wr t 24 cc 10 + t f tcl - 10+ t f ns ale rising edge after rd, wr t 26 cc -10 + t f -10+t f ns address/unlatched cs hold after rd, wr 2) t 28 cc 0 + t f 0+t f ns ale falling edge to latched cs t 38 cc -4 - t a 10 - t a -4 - t a 10 - t a ns ST10F163 45/58 latched cs low to valid data in t 39 sr 40 + t c + 2t a 3tcl - 20 +t c +2t a ns latched cs hold after rd, wr t 41 cc 6 + t f tcl - 14 +t f ns address setup to rdcs, wrcs (with rw-delay) t 82 cc 26 + 2t a 2tcl - 14 +2t a ns address setup to rdcs, wrcs (no rw-delay) t 83 cc 6 + 2t a tcl -14 +2t a ns rdcs to valid data in (with rw-delay) t 46 sr 16 + t c 2tcl - 24 +t c ns rdcs to valid data in (no rw-delay) t 47 sr 36 + t c 3tcl - 24 +t c ns rdcs, wrcs low time (with rw-delay) t 48 cc 30 + t c 2tcl - 10 +t c ns rdcs, wrcs low time (no rw-delay) t 49 cc 50 + t c 3tcl - 10 +t c ns data valid to wrcs t 50 cc 26 + t c 2tcl - 14 +t c ns data hold after rdcs t 51 sr00ns data float after rdcs (with rw-delay) t 53 sr 20 + t f 2tcl - 20 +t f ns data float after rdcs (no rw-delay) t 68 sr 0 + t f tcl - 20 +t f ns address hold after rdcs, wrcs t 55 cc -10 + t f -10+t f ns data hold after wrcs t 57 cc 6 + t f tcl - 14 +t f ns 1. rw-delay and t a refer to the following bus cycle. 2. read data are latched with the same clock edge that triggers the address change and the rising rd edge. therefore address changes before the end of rd have no impact on read cycles table 17 : demultiplexed bus characteristics (continued) parameter symbol max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. ST10F163 46/58 figure 18 : external memory cycle: demultiplexed bus, with/without read/write delay, normal ale data in data out t 38 ale csx p0 bus (d15-d8) d7-d0 read cycle rd p0 bus (d15-d8) d7-d0 write cycle wr(l), wrh t 5 t 16 t 39 t 41 t 18 t 14 t 22 t 12 clkout address a23-a16 (a15-a8) bhe t 17 t 13 t 15 t 12 t 13 t 21 t 20 t 81 t 80 t 26 t 24 t 17 t 6 t 41u t 6 t 80 t 81 t 28 ST10F163 47/58 figure 19 : external memory cycle: demultiplexed bus, with/without read/write delay, extended ale address ale rd write cycle wr(l), wrh t 5 t 16 t 39 t 41 t 14 t 24 t 6 t 38 t 20 csx clkout t 26 t 17 t 15 t 12 t 13 t 12 t 13 t 22 a23-a16 (a15-a8) bhe data in p0 bus (d15-d8) d7-d0 read cycle t 18 t 21 t 6 t 17 t 28 t 28 data out t 80 t 81 t 80 t 81 p0 bus (d15-d8) d7-d0 ST10F163 48/58 figure 20 : external memory cycle: demultiplexed bus, with/without read/write delay, normal ale, read/ write chip select data in data out ale p0 bus (d15-d8) d7-d0 read cycle rdcsx p0 bus (d15-d8) d7-d0 write cycle wrcsx t 5 t 16 t 51 t 46 t 50 t 48 clkout address a23-a16 (a15-a8) bhe t 17 t 49 t 47 t 48 t 49 t 68 t 53 t 83 t 82 t 26 t 57 t 55 t 6 t 82 t 83 ST10F163 49/58 figure 21 : external memory cycle: demultiplexed bus, no read/write delay, extended ale, read/write chip select address ale rdcsx write cycle wrcsx t 5 t 16 t 46 t 57 t 6 t 53 clkout t 26 t 17 t 47 t 48 t 49 t 48 t 49 t 50 a23-a16 (a15-a8) bhe data in p0 bus (d15-d8) d7-d0 read cycle t 51 t 68 t 55 data out t 82 t 83 t 82 t 83 p0 bus (d15-d8) d7-d0 ST10F163 50/58 xvi.4.12 - clkout and ready v dd =5v 10% v ss =0v t a = 0 to +70 cc l = 100 pf table 18 : clkout and ready characteristics parameter symbol max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. clkout cycle time t 29 cc 40 40 2tcl 2tcl ns clkout high time t 30 cc 14 tcl 6 ns clkout low time t 31 cc 10 tcl 10 ns clkout rise time t 32 cc44ns clkout fall time t 33 cc44ns clkout rising edge to ale falling edge t 34 cc 0 + t a 10 + t a 0+t a 10 + t a ns synchronous ready setup time to clkout t 35 sr1414ns synchronous ready hold time after clkout t 36 sr44ns asynchronous ready low time t 37 sr 58 2tcl + 18 ns asynchronous ready setup time 1) t 58 sr1414ns asynchronous ready hold time 1) t 59 sr44ns async. ready hold time after rd, wr high (demultiplexed bus) 2) t 60 sr 0 0 + 2t a + t c +t f 2) 0 tcl - 20 +2t a +t c +t f 2) ns 1. these timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. demultiplexed bus is the worst case. for multiplexed bus 2tcl are to be added to the maximum values. this adds even more time for deactivating ready. the 2t a and t c refer to the next following bus cycle, t f refers to the current bus cycle ST10F163 51/58 1. cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 2. the leading edge of the respective command depends on rw-delay. 3. ready sampled high at this sampling point generates a ready controlled waitstate, ready sampled low at this sampling point ter- minates the currently running bus cycle. 4. ready may be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr). 5. if the asynchronous ready signal does not fulfill the indicated setup and hold times with respect to clkout (e.g. because clkout is not enabled), it must fulfill t 37 in order to be safely synchronized. this is guaranteed, if ready is removed in response to the command (see note 4)). 6. multiplexed bus modes have a mux waitstate added after a bus cycle, and an additional mttc waitstate may be inserted here. for a multiplexed bus with mttc waitstate this delay is 2 clkout cycles, for a demultiplexed bus without mttc waitstate this delay is zero. 7. the next external bus cycle may start here. figure 22 : clkout and ready clkout ale t 30 t 34 sync ready t 35 t 36 t 35 t 36 async ready t 58 t 59 t 58 t 59 waitstate ready mux/tristate 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) command rd, wr t 60 4) see 6) 2) 7) 3) 3) ST10F163 52/58 xvi.4.13 - external bus arbitration 1. the ST10F163 will complete the currently running bus cycle before granting bus access. 2. this is the first possibility for breq to get active. 3. the cs outputs will be resistive high (pullup) after t 64 . v dd =5v 10% v ss =0v t a = 0 to +70 c c l (for port0, port1, port 4, ale, rd, wr, bhe, clkout) = 100 pf c l (for port 6, cs) = 100 pf parameter symbol max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. hold input setup time to clkout t 61 sr2020ns clkout to hlda high or breq low delay t 62 cc2020ns clkout to hlda low or breq high delay t 63 cc2020ns csx release t 64 cc2020ns csx drive t 65 cc -4 24 -4 24 ns other signals release t 66 cc2020ns other signals drive t 67 cc -4 24 -4 24 ns figure 23 : external bus arbitration, releasing the bus clkout hold t 61 hlda t 63 other signals t 66 1) csx (on p6.x) t 64 1) 2) breq t 62 3) ST10F163 53/58 figure 24 : external bus arbitration, (regaining the bus) 1. this is the last chance for breq to trigger the indicated regain-sequence. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be deactivated without the ST10F163 requesting the bus. 2. the next ST10F163 driven bus cycle may start here. clkout hold hlda other signals t 62 csx (on p6.x) t 67 t 62 1) 2) t 65 t 61 breq t 63 t 62 ST10F163 54/58 xvi.4.14 - synchronous serial port timing v cc =5v 10% v ss =0v t a = 0 to +70 c c l = 100 pf table 19 : synchronous serial port timing characteristics parameter symbol max. baudrate = 12.5 / 10 mbd variable baudrate = 0.5 to 12.5 mbd unit min. max. min. max. ssp clock cycle time t 200 cc 80 / 100 80 /100 4 tcl 512 tcl ns ssp clock high time t 201 cc 30 / 40 / t 200 /2 - 10 ns ssp clock low time t 202 cc 30 / 40 / t 200 /2 - 10 ns ssp clock rise time t 203 cc / 6 / 6 6 ns ssp clock fall time t 204 cc / 6 / 6 6 ns ce active before shift edge t 205 cc 30 / 40 / t 200 /2 - 10 ns ce inactive after latch edge t 206 cc 70 / 90 90 / 110 t 200 -10 t 200 +10 ns write data valid after shift edge t 207 cc / 10 / 10 10 ns write data hold after shift edge t 208 cc 0 / 0 / 0 ns write data hold after latch edge t 209 cc 34 / 44 46 / 56 t 200 /2 - 6 t 200 /2 + 6 ns read data active after latch edge t 210 sr 50 / 60 / t 200 /2 + 10 ns read data setup time before latch edge t 211 sr 20 / 20 / 20 ns read data hold time after latch edge t 212 sr 0 / 0 / 0 ns figure 25 : ssp write timing t 204 t 203 sspclk sspcex sspdat t 205 t 207 t 207 t 207 t 208 t 209 t 206 1st bit last bit 2nd bit t 200 t 201 t 202 1) 3) 2) ST10F163 55/58 the transition of shift and latch edge of sspclk is programmable. this figure uses the falling edge as shift edge (drawn bold). the bit timing is repeated for all bits to be transmitted or received. the active level of the chip enable lines is programmable. this figure uses an active low ce (drawn bold). at the end of a transmission or reception the ce signal is disabled in single transfer mode. in continuous transfer mode it remains active. figure 26 : ssp read timing t 211 sspclk sspcex sspdat t 209 t 206 last wr. bit lst.in bit 1) 3) 2) t 212 1st.in bit t 210 ST10F163 56/58 xvii - package mechanical data xviii - ordering information figure 27 : package outline tqfp100 (14 x 14 mm) dimensions millimeters inches min. typ. max. min. typ. max. a 1.60 0.063 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 15.75 16.00 16.25 0.620 0.630 0.640 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 12.00 0.472 e 15.75 16.00 16.25 0.620 0.630 0.640 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 0.50 0.020 number of pins nd 25 ne 25 n 100 salestype temperature range package ST10F163bt1 0 cto70 c tqfp100 (14x 14) 76 100 50 d3 e 26 1 25 75 51 c b a1 a2 a d1 d e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,075 mm 0.03 inch seating plane ST10F163 57/58 xix - revision history the following changes have been made from ST10F163 data sheet revision 5 to create this revision 6: table added table 8 on page 20 table added table 9 on page 21 table added table 10 on page 23 table added table 11 on page 24 table added table 12 on page 25 table added table 3 on page 11 table added table 4 on page 11 table added table 5 on page 12 presentation changed figure 14 to figure 21 specification changed t 22 from 2tcl-16+t c to 2tcl-20+t c specification changed t 8 -t 9 replaced with t 80 -t 81 for demultiplexed bus specification changed t 42 -t 43 replaced with t 82 -t 83 for demultiplexed bus specification changed t 35 from 10ns to 14ns specification changed t 36 and t 59 from 0ns to 4ns specification changed t 37 from omin 54ns, var min 2tcl+14nso to omin 58ns, var min 2tcl+18nso specification changed table 15: input hight voltage rstin, min. 0.6v dd chnaged to 0.7v dd ST10F163 58/58 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - 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